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? 2001-2013 microchip technology inc. ds21669d-page 1 mcp6041/2/3/4 features ? low quiescent current: 600 na/amplifier (typical) ? rail-to-rail input/output ? gain bandwidth product: 14 khz (typical) ? wide supply voltage range: 1.4v to 6.0v ? unity gain stable ? available in single, dual, and quad ? chip select (cs ) with mcp6043 ? available in 5-lead and 6-lead sot-23 packages ? temperature ranges: - industrial: -40c to +85c - extended: -40c to +125c applications ? toll booth tags ? wearable products ? temperature measurement ? battery powered design aids ? spice macro models ?filterlab ? software ? maps (microchip advanced part selector) ? analog demonstration and evaluation boards ? application notes related devices ? mcp6141/2/3/4: g = +10 stable op amps typical application description the mcp6041/2/3/4 family of operational amplifiers (op amps) from microchip technology inc. operate with a single supply voltage as low as 1.4v, while drawing less than 1 a (maximum) of quiescent current per amplifier. these devices are also designed to support rail-to-rail input and output operation. this combination of features supports battery-powered and portable applications. the mcp6041/2/3/4 amplifiers have a gain-bandwidth product of 14 khz (typical) and are unity gain stable. these specifications make these op amps appropriate for low frequency applications, such as battery current monitoring and sensor conditioning. the mcp6041/2/3/4 family operational amplifiers are offered in single (mcp6041), single with chip select (cs ) (mcp6043), dual (mcp6042), and quad (mcp6044) configurations. the mcp6041 device is available in the 5-lead sot-23 package, and the mcp6043 device is available in the 6-lead sot-23 package. package types v dd i dd mcp604x 100 k ? 1m ? 1.4v v out high side battery current sensor 10 ? to 6.0v i dd v dd v out ? 10 v/v ?? 10 ? ?? ? ----------------------------------------- - = v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc nc nc mcp6041 pdip, soic, msop mcp6042 pdip, soic, msop mcp6043 pdip, soic, msop mcp6044 pdip, soic, tssop v ina + v ina ? v ss v outb v inb ? 1 2 3 4 8 7 6 5 v inb + v dd v outa v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc cs nc v ina + v ina ? v dd v ind ? v ind + 1 2 3 4 14 13 12 11 v ss v outd v outa v inb ? v inb + v outb v inc + v inc ? 5 6 7 10 9 8 v outc v in + v ss v in ? 1 2 3 5 4 v dd v out mcp6041 sot-23-5 v in + v ss v in ? 1 2 3 6 4 v dd v out mcp6043 sot-23-6 5 cs 600 na, rail-to-rail input/output op amps
mcp6041/2/3/4 ds21669d-page 2 ? 2001-2013 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ?v ss ........................................................................7.0v current at input pins .....................................................2 ma analog inputs (v in +, v in ?) ............. v ss ? 1.0v to v dd +1.0v all other inputs and outputs .......... v ss ? 0.3v to v dd +0.3v difference input voltage ...................................... |v dd ?v ss | output short circuit current ..................................continuous current at output and supply pins ............................30 ma storage temperature....................................?65c to +150c junction temperature.................................................. +150c esd protection on all pins (hbm; mm) ???????????????? ?? 4 kv; 200v ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ?? see section 4.1 ?rail-to-rail input? dc electrical characteristics electrical characteristics: unless otherwise indicated, v dd = +1.4v to +5.5v, v ss = gnd, t a = 25c, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, and r l = 1 m ?? to v l (refer to figure 1-2 and figure 1-3 ). parameters sym min typ max units conditions input offset input offset voltage v os -3 ? +3 mv v cm = v ss drift with temperature ? v os / ? t a ?2?v/cv cm = v ss , t a = -40c to +85c ? v os / ? t a ?15?v/cv cm = v ss , t a = +85c to +125c power supply rejection psrr 70 85 ? db v cm = v ss input bias current and impedance input bias current i b ?1?pa industrial temperature i b ? 20 100 pa t a = +85 extended temperature i b ? 1200 5000 pa t a = +125 input offset current i os ?1?pa common mode input impedance z cm ?10 13 ||6 ? ? ||pf differential input impedance z diff ?10 13 ||6 ? ? ||pf common mode common-mode input range v cmr v ss ? 0.3 ? v dd +0.3 v common-mode rejection ratio cmrr 62 80 ? db v dd = 5v, v cm = -0.3v to 5.3v cmrr 60 75 ? db v dd = 5v, v cm = 2.5v to 5.3v cmrr 60 80 ? db v dd = 5v, v cm = -0.3v to 2.5v open-loop gain dc open-loop gain (large signal) a ol 95 115 ? db r l = 50 k ? to v l , v out = 0.1v to v dd ? 0.1v output maximum output voltage swing v ol , v oh v ss +10 ? v dd ? 10 mv r l = 50 k ? to v l , 0.5v input overdrive linear region output voltage swing v ovr v ss + 100 ? v dd ? 100 mv r l = 50 k ? to v l , a ol ?? 95 db output short circuit current i sc ?2?mav dd = 1.4v i sc ?20?mav dd = 5.5v power supply supply voltage v dd 1.4 ? 6.0 v ( note 1 ) quiescent current per amplifier i q 0.3 0.6 1.0 a i o = 0 note 1: all parts with date codes november 2007 and la ter have been screened to ensure operation at v dd = 6.0v. however, the other minimum and maximum specificatio ns are measured at 1.4v and/or 5.5v.
? 2001-2013 microchip technology inc. ds21669d-page 3 mcp6041/2/3/4 ac electrical characteristics mcp6043 chip select (cs ) electrical characteristics figure 1-1: chip select (cs ) timing diagram (mcp6043 only). electrical characteristics: unless otherwise indicated, v dd = +1.4v to +5.5v, v ss = gnd, t a = 25c, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l = 1 m ?? to v l , and c l = 60 pf (refer to figure 1-2 and figure 1-3 ). parameters sym min typ max units conditions ac response gain bandwidth product gbwp ? 14 ? khz slew rate sr ? 3.0 ? v/ms phase margin pm ? 65 ? g = +1 v/v noise input voltage noise e ni ?5.0?v p-p f = 0.1 hz to 10 hz input voltage noise density e ni ? 170 ? nv/ ? hz f = 1 khz input current noise density i ni ?0.6?fa/ ? hz f = 1 khz electrical characteristics: unless otherwise indicated, v dd = +1.4v to +5.5v, v ss = gnd, t a = 25c, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l = 1 m ?? to v l , and c l = 60 pf (refer to figure 1-2 and figure 1-3 ). parameters sym min typ max units conditions cs low specifications cs logic threshold, low v il v ss ?v ss +0.3 v cs input current, low i csl ?5?pacs = v ss cs high specifications cs logic threshold, high v ih v dd ?0.3 ? v dd v cs input current, high i csh ?5?pacs = v dd cs input high, gnd current i ss ?-20? pacs = v dd amplifier output leakage, cs high i oleak ?20?pacs = v dd dynamic specifications cs low to amplifier output turn-on time t on ? 2 50 ms g = +1v/v, cs = 0.3v to v out = 0.9v dd /2 cs high to amplifier output high-z t off ? 10 ? s g = +1v/v, cs = v dd ?0.3v to v out = 0.1v dd /2 hysteresis v hyst ?0.6? vv dd = 5.0v v il high-z t on v ih cs t off v out -20 pa high-z i ss i cs 5pa -20 pa -0.6 a (typical) (typical) (typical) (typical)
mcp6041/2/3/4 ds21669d-page 4 ? 2001-2013 microchip technology inc. temperature characteristics 1.1 test circuits the test circuits used for the dc and ac tests are shown in figure 1-2 and figure 1-3 . the bypass capacitors are laid out according to the rules discussed in section 4.6 ?supply bypass? . figure 1-2: ac and dc test circuit for most non-inverting gain conditions. figure 1-3: ac and dc test circuit for most inverting gain conditions. electrical characteristics: unless otherwise indicated, v dd = +1.4v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +85 c industrial temperature parts t a -40 ? +125 c extended temperature parts operating temperature range t a -40 ? +125 c ( note 1 ) storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot-23 ? ja ? 256 ? c/w thermal resistance, 6l-sot-23 ? ja ? 230 ? c/w thermal resistance, 8l-pdip ? ja ?85?c/w thermal resistance, 8l-soic ? ja ? 163 ? c/w thermal resistance, 8l-msop ? ja ? 206 ? c/w thermal resistance, 14l-pdip ? ja ?70?c/w thermal resistance, 14l-soic ? ja ? 120 ? c/w thermal resistance, 14l-tssop ? ja ? 100 ? c/w note 1: the mcp6041/2/3/4 family of industrial temperature op am ps operates over this ex tended range, but with reduced performance. in any case, the in ternal junction temperature (t j ) must not exceed the absolute maximum specification of +150c. v dd mcp604x r g r f r n v out v in v dd /2 1f c l r l v l 0.1 f v dd mcp604x r g r f r n v out v dd /2 v in 1f c l r l v l 0.1 f
? 2001-2013 microchip technology inc. ds21669d-page 5 mcp6041/2/3/4 2.0 typical performance curves note: unless otherwise indicated, t a =+25c, v dd = +1.4v to +6.0v, v ss = gnd, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l =1m ? to v l , and c l =60pf. figure 2-1: input offset voltage. figure 2-2: input offset voltage drift with t a = -40c to +85c. figure 2-3: input offset voltage vs. common mode input voltage with v dd =1.4v. figure 2-4: input offset voltage drift with t a = +85c to +125c and v dd =1.4v. figure 2-5: input offset voltage drift with t a = +25c to +125c and v dd =5.5v. figure 2-6: input offset voltage vs. common mode input voltage with v dd =5.5v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 1% 2% 3% 4% 5% 6% 7% 8% 9% 10% -3 -2 -1 0 1 2 3 input offset voltage (mv) percentage of occurrences 1124 samples v dd = 1.4v and 5.5v v cm = v ss 0% 1% 2% 3% 4% 5% 6% 7% 8% 9% 10% 11% 12% -10-8-6-4-20246810 input offset voltage drift (v/c) percentage of occurrences 1124 samples t a = -40c to +85c v dd = 1.4v v cm = v ss -2000 -1500 -1000 -500 0 500 1000 1500 2000 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 common mode input voltage (v) input offset voltage (v) v dd = 1.4v representative part t a = +125c t a = +85c t a = +25c t a = -40c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% -32 -28 -24 -20 -16 -12 -8 -4 0 4 input offset voltage drift (v/c) percentage of occurrences 245 samples 1 representative lot t a = +85c to +125c v dd = 1.4v v cm = v ss 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 24% -32 -28 -24 -20 -16 -12 -8 -4 0 4 input offset voltage drift (v/c) percentage of occurrences 239 samples 1 representative lot t a = +85c to +125c v dd = 5.5v v cm = v ss -2000 -1500 -1000 -500 0 500 1000 1500 2000 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input offset voltage (v) v dd = 5.5v representative part t a = +125c t a = +85c t a = +25c t a = -40c
mcp6041/2/3/4 ds21669d-page 6 ? 2001-2013 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.4v to +6.0v, v ss = gnd, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l =1m ? to v l , and c l =60pf. figure 2-7: input offset voltage vs. output voltage. figure 2-8: input noise voltage density vs. frequency. figure 2-9: cmrr, psrr vs. frequency. figure 2-10: the mcp6041/2/3/4 family shows no phase reversal. figure 2-11: input noise voltage density vs. common mode input voltage. figure 2-12: cmrr, psrr vs. ambient temperature. 250 300 350 400 450 500 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) input offset voltage (v) v dd = 5.5v v dd = 1.4v 100 1000 0.1 1 10 100 1000 frequency (hz) input noise voltage density (nv/hz) 20 30 40 50 60 70 80 90 0.1 1 10 100 1000 frequency (hz) cmrr, psrr (db) psrr? psrr+ cmrr referred to input -1 0 1 2 3 4 5 6 0 5 10 15 20 25 time (5 ms/div) input, output voltages (v) v in v dd = 5.0v g = +2 v/v v out 0 50 100 150 200 250 300 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input noise voltage density (nv/ hz) f = 1 khz v dd = 5.0v 70 75 80 85 90 95 100 -50 -25 0 25 50 75 100 125 mient temperature (c) srr, cmrr (db) srr (v cm = v ss ) cmrr (v dd = 5.0v, v cm = -0.3v to +5.3v)
? 2001-2013 microchip technology inc. ds21669d-page 7 mcp6041/2/3/4 note: unless otherwise indicated, t a =+25c, v dd = +1.4v to +6.0v, v ss = gnd, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l =1m ? to v l , and c l =60pf. figure 2-13: input bias, offset currents vs. ambient temperature. figure 2-14: open-loop gain, phase vs. frequency. figure 2-15: dc open-loop gain vs. power supply voltage. figure 2-16: input bias, offset currents vs. common mode input voltage. figure 2-17: dc open-loop gain vs. load resistance. figure 2-18: dc open-loop gain vs. output voltage headroom. 0.1 1 10 100 1000 10000 45 55 65 75 85 95 105 115 125 ambient temperature (c) input bias and offset currents (pa) | i os | i b v dd = 5.5v v cm = v dd 0.1 1 10 100 1k 10k -20 0 20 40 60 80 100 120 1.e- 03 1.e- 02 1.e- 01 1.e+ 00 1.e+ 01 1.e+ 02 1.e+ 03 1.e+ 04 1.e+ 05 frequency (hz) open-loop gain (db) -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () 0.001 0.01 0.1 1 10 100 1k 10k 100k gain phase 80 90 100 110 120 130 140 1.01.52.02.53.03.54.04.55.05.5 power supply voltage (v) dc open-loop gain (db) r l = 50 k ? v dd = 5.0v v out = 0.1v to v dd - 0.1v 0.1 1 10 100 1000 10000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias and offset currents (pa) v dd = 5.5v | i os | i b 0.1 1 10 100 1k 10k t a = +125c t a = +85c 60 70 80 90 100 110 120 130 1.e+02 1.e+03 1.e+04 1.e+05 load resistance ( ) dc open-loop gain (db) v dd = 1.4v 100 1k 10k 100k v out = 0.1v to v dd C 0.1v v dd = 5.5v 80 90 100 110 120 130 140 0.00 0.05 0.10 0.15 0.20 0.25 output voltage headroom; v dd ? v oh or v ol ? v ss (v) dc open-loop gain (db) r l = 50 k v dd = 5.5v v dd = 1.4v
mcp6041/2/3/4 ds21669d-page 8 ? 2001-2013 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.4v to +6.0v, v ss = gnd, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l =1m ? to v l , and c l =60pf. figure 2-19: channel-to-channel separation vs. frequency (mcp6042 and mcp6044 only). figure 2-20: gain bandwidth product, phase margin vs. ambient temperature with v dd =1.4v. figure 2-21: quiescent current vs. power supply voltage. figure 2-22: gain bandwidth product, phase margin vs. common mode input voltage. figure 2-23: gain bandwidth product, phase margin vs. ambient temperature with v dd =5.5v. figure 2-24: output short circuit current vs. power supply voltage. 60 70 80 90 100 110 120 130 1.e+02 1.e+03 1.e+04 frequency (hz) channel to channel separation (db) 100 1k 10k input referred 0 2 4 6 8 10 12 14 16 18 -50 -25 0 25 50 75 100 125 ambient temperature (c) gain bandwidth product (khz) 0 10 20 30 40 50 60 70 80 90 phase margin () pm (g = +1) gbwp v dd = 1.4v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) quiescent current (a/amplifier) t a = +125c t a = +85c t a = +25c t a = -40c 0 2 4 6 8 10 12 14 16 18 20 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage gain bandwidth product (khz) 0 10 20 30 40 50 60 70 80 90 100 phase margin () pm (g = +1) gbwp v dd = 5.0v r l = 100 k ? 0 2 4 6 8 10 12 14 16 18 -50 -25 0 25 50 75 100 125 ambient temperature (c) gain bandwidth product (khz) 0 10 20 30 40 50 60 70 80 90 phase margin () pm (g = +1) gbwp v dd = 5.5v 0 5 10 15 20 25 30 35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) output short circuit current magnitude (ma) t a = -40c t a = +25c t a = +85c t a = +125c
? 2001-2013 microchip technology inc. ds21669d-page 9 mcp6041/2/3/4 note: unless otherwise indicated, t a =+25c, v dd = +1.4v to +6.0v, v ss = gnd, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l =1m ? to v l , and c l =60pf. figure 2-25: output voltage headroom vs. output current magnitude. figure 2-26: slew rate vs. ambient temperature. figure 2-27: small signal non-inverting pulse response. figure 2-28: output voltage headroom vs. ambient temperature. figure 2-29: maximum output voltage swing vs. frequency. figure 2-30: small signal inverting pulse response. 1 10 100 1000 0.01 0.1 1 10 output current magnitude (ma) output voltage headroom; v dd ? v oh or v ol ? v ss (mv) v dd ? v oh v ol ? v ss 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/ms) high-to-low low-to-high v dd = 1.4v v dd = 5.5v -25 -20 -15 -10 -5 0 5 10 15 20 25 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 time (100 s/div) output voltage (5mv/div) g = +1 v/v r l = 50 k ? ? ?
mcp6041/2/3/4 ds21669d-page 10 ? 2001-2013 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.4v to +6.0v, v ss = gnd, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l =1m ? to v l , and c l =60pf. figure 2-31: large signal non-inverting pulse response. figure 2-32: chip select (cs ) to amplifier output response time (mcp6043 only). figure 2-33: input current vs. input voltage (below v ss ). figure 2-34: large signal inverting pulse response. figure 2-35: chip select (cs ) hysteresis (mcp6043 only). 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 012345678910 time (1 ms/div) output voltage (v) v dd = 5.0v g = +1 v/v r l = 50 k ? -20.0 -17.5 -15.0 -12.5 -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 012345678910 time (1 ms/div) cs voltage (v) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output voltage (v) v dd = 5.0v v out high-z high-z output on cs 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) input current magnitude (a) +125c +85c +25c -40c 10m 1m 100 10 1 100n 10n 1n 100p 10p 1p 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 012345678910 time (1 ms/div) output voltage (v) v dd = 5.0v g = -1 v/v r l = 50 k ?
? 2001-2013 microchip technology inc. ds21669d-page 11 mcp6041/2/3/4 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 analog outputs the output pins are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs are high-imped- ance cmos inputs with low bias currents. 3.3 chip select digital input this is a cmos, schmitt-triggered input that places the part into a low power mode of operation. 3.4 power supply pins the positive power supply pin (v dd ) is 1.4v to 6.0v higher than the negative power supply pin (v ss ). for normal operation, the other pins are at voltages between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors. mcp6041 mcp6042 mcp6043 mcp6044 symbol description pdip, soic, msop sot-23-5 pdip, soic, msop pdip, soic, msop sot-23-6 pdip, soic, tssop 61 161 1v out ,v outa analog output (op amp a) 24 224 2v in ?, v ina ? inverting input (op amp a) 33 333 3v in +, v ina + non-inverting input (op amp a) 75 876 4 v dd positive power supply ?? 5?? 5 v inb + non-inverting input (op amp b) ?? 6?? 6 v inb ? inverting input (op amp b) ?? 7?? 7v outb analog output (op amp b) ?? ??? 8v outc analog output (op amp c) ?? ??? 9 v inc ? inverting input (op amp c) ?? ??? 10v inc + non-inverting input (op amp c) 42 442 11v ss negative power supply ?? ??? 12v ind + non-inverting input (op amp d) ?? ??? 13v ind ? inverting input (op amp d) ?? ??? 14v outd analog output (op amp d) ?? ?8 5 ? cs chip select 1, 5, 8 ? ? 1, 5 ? ? nc no internal connection
mcp6041/2/3/4 ds21669d-page 12 ? 2001-2013 microchip technology inc. 4.0 applications information the mcp6041/2/3/4 family of op amps is manufactured using microchip?s state of the art cmos process. these op amps are unity gain stable and suitable for a wide range of general purpose, low-power applica- tions. see microchip?s related mcp6141/2/3/4 family of op amps for applications, at a gain of 10 v/v or higher, needing greater bandwidth. 4.1 rail-to-rail input 4.1.1 phase reversal the mcp6041/2/3/4 op amps are designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-10 shows an input voltage exceeding both supplies with no phase inversion. 4.1.2 input voltage and current limits the esd protection on the inputs can be depicted as shown in figure 4-1 . this structure was chosen to protect the input transistors, and to minimize input bias current (i b ). the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick esd events within the specified limits. figure 4-1: simplified analog input esd structures. in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see absolute maxi- mum ratings ? at the beginning of section 1.0 ?elec- trical characteristics? ). figure 4-2 shows the recommended approach to protecting these inputs. the internal esd diodes prevent the input pins (v in + and v in ?) from going too far below ground, and the resistors r 1 and r 2 limit the possible current drawn out of the input pins. diodes d 1 and d 2 prevent the input pins (v in + and v in ?) from going too far above v dd , and dump any currents onto v dd . when implemented as shown, resistors r 1 and r 2 also limit the current through d 1 and d 2 . figure 4-2: protecting the analog inputs. it is also possible to connect the diodes to the left of the resistor r 1 and r 2 . in this case, the currents through the diodes d 1 and d 2 need to be limited by some other mechanism. the resistors then serve as in-rush current limiters; the dc current into the input pins (v in + and v in ?) should be very small. a significant amount of current can flow out of the inputs (through the esd diodes) when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-33 . applications that are high impedance may need to limit the useable voltage range. 4.1.3 normal operation the input stage of the mcp6041/2/3/4 op amps uses two differential input stages in parallel. one operates at a low common mode input voltage (v cm ), while the other operates at a high v cm . with this topology, the device operates with a v cm up to 300 mv above v dd and 300 mv below v ss . the input offset voltage is measured at v cm =v ss ?0.3v and v dd + 0.3v to ensure proper operation. there are two transitions in input behavior as v cm is changed. the first occurs, when v cm is near v ss + 0.4v, and the second occurs when v cm is near v dd ?0.5v (see figure 2-3 and figure 2-6 ). for the best distortion performance with non-inverting gains, avoid these regions of operation. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in ? v 1 mcp604x r 1 v dd d 1 r 1 > v ss ? (minimum expected v 1 ) 2ma v out r 2 > v ss ? (minimum expected v 2 ) 2ma v 2 r 2 d 2 r 3
? 2001-2013 microchip technology inc. ds21669d-page 13 mcp6041/2/3/4 4.2 rail-to-rail output there are two specifications that describe the output swing capability of the mcp6041/2/3/4 family of op amps. the first specification (maximum output voltage swing) defines the absolute maximum swing that can be achieved under the specified load condition. thus, the output voltage swings to within 10 mv of either sup- ply rail with a 50 k ? load to v dd /2. figure 2-10 shows how the output voltage is limited when the input goes beyond the linear region of operation. the second specification that describes the output swing capability of these amplifiers is the linear output voltage range. this specification defines the maxi- mum output swing that can be achieved while the amplifier still operates in its linear region. to verify linear operation in this range, the large signal dc open-loop gain (a ol ) is measured at points inside the supply rails. the measurement must meet the specified a ol condition in the specification table. 4.3 output loads and battery life the mcp6041/2/3/4 op amp family has outstanding quiescent current, which supports battery-powered applications. there is minimal quiescent current glitching when chip select (cs ) is raised or lowered. this prevents excessive current draw, and reduced battery life, when the part is turned off or on. heavy resistive loads at the output can cause excessive battery drain. driving a dc voltage of 2.5v across a 100 k ? load resistor will cause the supply cur- rent to increase by 25 a, depleting the battery 43 times as fast as i q (0.6 a, typical) alone. high frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current. for instance, a 0.1 f capacitor at the output presents an ac impedance of 15.9 k ? (1/2 ? fc) to a 100 hz sinewave. it can be shown that the average power drawn from the battery by a 5.0 v p-p sinewave (1.77 v rms ), under these conditions, is equation 4-1: this will drain the battery 18 times as fast as i q alone. 4.4 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. a unity gain buffer (g = +1) is the most sensitive to capacitive loads, although all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 60 pf when g = +1), a small series resistor at the output (r iso in figure 4-3 ) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-3: output resistor, r iso stabilizes large capacitive loads. figure 4-4 gives recommended r iso values for different capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n ), where g n is the circuit?s noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n =+2v/v). figure 4-4: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot. modify r iso ?s value until the response is reasonable. bench evaluation and simulations with the mcp6041/2/3/4 spice macro model are helpful. p supply = (v dd - v ss ) (i q + v l(p-p) f c l ) = (5v)(0.6 a + 5.0v p-p 100hz 0.1f) = 3.0 w + 50 w v in mcp604x r iso v out c l 1,000 10,000 100,000 1.e+01 1.e+02 1.e+03 1.e+04 normalized load capacitance; c l /g n (f) recommended r iso ( ) 10p 1k 100k 100p g n = +1 g n = +2 g n +5 10k 10n 1n
mcp6041/2/3/4 ds21669d-page 14 ? 2001-2013 microchip technology inc. 4.5 mcp6043 chip select the mcp6043 is a single op amp with chip select (cs ). when cs is pulled high, the supply current drops to 50 na (typical) and flows through the cs pin to v ss . when this happens, the amplifier output is put into a high impedance state. by pulling cs low, the amplifier is enabled. if the cs pin is left floating, the amplifier may not operate properly. figure 1-1 shows the output voltage and supply current response to a cs pulse. 4.6 supply bypass with this family of operational amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good high frequency performance. it can use a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor is not required for most applications and can be shared with nearby analog parts. 4.7 unused op amps an unused op amp in a quad package (mcp6044) should be configured as shown in figure 4-5 . these circuits prevent the output from toggling and causing crosstalk. circuit a sets the op amp at its minimum noise gain. the resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. circuit b uses the minimum number of components and operates as a comparator, but it may draw more current. figure 4-5: unused op amps. 4.8 pcb surface leakage in applications where low input bias current is critical, printed circuit board (pcb) surface leakage effects need to be considered. surface leakage is caused by humidity, dust or other contamination on the board. under low humidity conditions, a typical resistance between nearby traces is 10 12 ? . a 5v difference would cause 5 pa of current to flow, which is greater than the mcp6041/2/3/4 family?s bias current at +25c (1 pa, typical). the easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). the guard ring is biased at the same voltage as the sensitive pin. figure 4-6 shows an example of this type of layout. figure 4-6: example guard ring layout for inverting gain. 1. non-inverting gain and unity gain buffer: a) connect the non-inverting pin (v in +) to the input with a wire that does not touch the pcb surface. b) connect the guard ring to the inverting input pin (v in ?). this biases the guard ring to the common mode input voltage. 2. inverting gain and transimpedance gain (convert current to voltage, such as photo detectors) amplifiers: a) connect the guard ring to the non-inverting input pin (v in +). this biases the guard ring to the same reference voltage as the op amp (e.g., v dd /2 or ground). b) connect the inverting pin (v in ?) to the input with a wire that does not touch the pcb surface. v dd v dd ? mcp6044 (a) ? mcp6044 (b) r 1 r 2 v dd v ref v ref v dd r 2 r 1 r 2 + ------------------ ? = guard ring v in ?v in +
? 2001-2013 microchip technology inc. ds21669d-page 15 mcp6041/2/3/4 4.9 application circuits 4.9.1 battery current sensing the mcp6041/2/3/4 op amps? common mode input range, which goes 0.3v beyond both supply rails, supports their use in high-side and low-side battery current sensing applications. the very low quiescent current (0.6 a, typical) helps prolong battery life, and the rail-to-rail output supports detection low currents. figure 4-7 shows a high-side battery current sensor circuit. the 10 ? resistor is sized to minimize power losses. the battery current (i dd ) through the 10 ? resistor causes its top terminal to be more negative than the bottom terminal. this keeps the common mode input voltage of the op amp below v dd , which is within its allowed range. the output of the op amp will also be below v dd , which is within its maximum output voltage swing specification. . figure 4-7: high-side battery current sensor. 4.9.2 instrumentation amplifier the mcp6041/2/3/4 op amp is well suited for conditioning sensor signals in battery-powered applications. figure 4-8 shows a two op amp instru- mentation amplifier, using the mcp6042, that works well for applications requiring rejection of common mode noise at higher gains. the reference voltage (v ref ) is supplied by a low impedance source. in single supply applications, v ref is typically v dd /2. . figure 4-8: two op amp instrumentation amplifier. v dd i dd mcp604x 100 k ? 1m ? 1.4v v out 10 ? to 6.0v i dd v dd v out ? 10 v/v ?? 10 ? ?? ? ----------------------------------------- - = v out v 1 v 2 ? ?? 1 r 1 r 2 ----- - 2 r 1 r g --------- ++ ?? ?? v ref + = v ref r 1 r 2 r 2 r 1 v out r g v 2 v 1 ? mcp6042 ? mcp6042
mcp6041/2/3/4 ds21669d-page 16 ? 2001-2013 microchip technology inc. 5.0 design aids microchip provides the basic design tools needed for the mcp6041/2/3/4 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp6041/2/3/4 op amps is available on the microchip web site at www.microchip.com . this model is intended to be an initial design tool that works well in the op amp?s linear region of operation over the temperature range. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchip?s filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the microchip web site at www.microchip.com/filterlab , the filterlab design tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance. 5.3 maps (microchip advanced part selector) maps is a software tool that helps semiconductor professionals efficiently identify microchip devices that fit a particular design requirement. available at no cost from the microchip website at www.microchip.com/ maps , the maps is an overall selection tool for microchip?s product portfolio that includes analog, memory, mcus and dscs. using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase, and sampling of microchip parts. 5.4 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demonstration and evaluation boards that are designed to help you achieve faster time to market. for a complete listing of these boards and their corresponding user?s guides and technical information, visit the microchip web site at www.microchip.com/ analogtools . some boards that are especially useful are: ? p/n soic8ev: 8-pin soic/msop/tssop/dip evaluation board ? p/n soic14ev: 14-pin soic/tssop/dip evalu- ation board ? mcp6xxx amplifier evaluation board 1 ? mcp6xxx amplifier evaluation board 2 ? mcp6xxx amplifier evaluation board 3 ? mcp6xxx amplifier evaluation board 4 ? active filter demo board kit 5.5 application notes the following microchip application notes are avail- able on the microchip web site at www.microchip.com/ appnotes and are recommended as supplemental ref- erence resources: adn003: ?select the right operational amplifier for your filtering circuits?, ds21821 an722: ?operational amplifier topologies and dc specifications?, ds00722 an723: ?operational amplifier ac specifications and applications?, ds00723 an884: ?driving capacitive loads with op amps?, ds00884 an990: ?analog sensor conditioning circuits ? an overview?, ds00990 these application notes and others are listed in the design guide: ?signal chain design guide?, ds21825
? 2001-2013 microchip technology inc. ds21669d-page 17 mcp6041/2/3/4 6.0 packaging information 6.1 package marking information 8-lead msop example : xxxxxx ywwnnn 6043i 304256 5-lead sot-23 ( mcp6041 ) example: xxnn 7x25 device i-temp code e-temp code mcp6041/t-e/ot spnn 7xnn note: parts with date codes prior to november 2012 have their package markings in the sbnn format. 6-lead sot-23 ( mcp6043) example: xxnn sc25 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e device i-temp code e-temp code mcp6043t-e/ch scnn sdnn xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example : 8-lead soic (150 mil) example : xxxxxxxx xxxxyyww nnn mcp6041 i/p256 1304 mcp6042 i/sn1304 256 mcp6041 i/p 256 1304 mcp6042i sn 1304 256 3 e or or 3 e
mcp6041/2/3/4 ds21669d-page 18 ? 2001-2013 microchip technology inc. package marking information (continued) 14-lead pdip (300 mil) ( mcp6044 )example : xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn mcp6044 -i/p 1304256 mcp6044 1304256 e/p 3 e or 14-lead tssop ( mcp6044 ) example : 14-lead soic (150 mil) ( mcp6044 ) example: xxxxxxxxxx yywwnnn xxxxxxxx yyww nnn 6044st 1304 256 xxxxxxxxxx mcp6044isl 1304256 mcp6044 1304256 e/sl ^^ or 3 e 6044est 1304 256 or i/sl ^^ 3 e
? 2001-2013 microchip technology inc. ds21669d-page 19 mcp6041/2/3/4 n b e e1 d 1 2 3 e e1 a a1 a2 c l l1
mcp6041/2/3/4 ds21669d-page 20 ? 2001-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2001-2013 microchip technology inc. ds21669d-page 21 mcp6041/2/3/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6041/2/3/4 ds21669d-page 22 ? 2001-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2001-2013 microchip technology inc. ds21669d-page 23 mcp6041/2/3/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6041/2/3/4 ds21669d-page 24 ? 2001-2013 microchip technology inc. n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c
? 2001-2013 microchip technology inc. ds21669d-page 25 mcp6041/2/3/4 n e1 d note 1 12 3 e c eb a2 l a a1 b1 be
mcp6041/2/3/4 ds21669d-page 26 ? 2001-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2001-2013 microchip technology inc. ds21669d-page 27 mcp6041/2/3/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6041/2/3/4 ds21669d-page 28 ? 2001-2013 microchip technology inc.
? 2001-2013 microchip technology inc. ds21669d-page 29 mcp6041/2/3/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6041/2/3/4 ds21669d-page 30 ? 2001-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2001-2013 microchip technology inc. ds21669d-page 31 mcp6041/2/3/4
mcp6041/2/3/4 ds21669d-page 32 ? 2001-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2001-2013 microchip technology inc. ds21669d-page 33 mcp6041/2/3/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6041/2/3/4 ds21669d-page 34 ? 2001-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2001-2013 microchip technology inc. ds21669d-page 35 mcp6041/2/3/4 appendix a: revision history revision d (march 2013) the following is the list of modifications: 1. updated the boards list in section 5.4 ?analog demonstration and evaluation boards? . 2. removed the mindi? circuit designer & simulator section. 3. updated the e-temp code value for the 5-lead sot-23 package in section 6.0 ?packaging information? . revision c (february 2008) the following is the list of modifications: 1. updated figure 2-4 and figure 2-5 . 2. updated trademark and sales listing pages. 3. expanded this op amp family: 4. added the sot-23-6 package for the mcp6043 op amp with chip select. 5. added extended temperature (-40c to +125c) parts. 6. expanded analog input absolute max voltage range (applies retroactively). 7. expanded operating v dd to a maximum of 6.0v. 8. section 1.0 ?electrical characteristics? updated. 9. section 2.0 ?typical performance curves? updated. 10. section 3.0 ?pin descriptions? added. 11. section 4.0 ?applications information? added. 12. added section 4.7 ?unused op amps? . 13. updated input stage explanation. 14. section 5.0 ?design aids? updated. 15. section 6.0 ?packaging information? updated. 16. added sot-23-6 package. 17. corrected package marking information. 18. appendix a: ?revision history? added. revision b (june 2002) the following is the list of modifications. ? undocumented changes. revision a (august 2001) ? original data sheet release.
mcp6041/2/3/4 ds21669d-page 36 ? 2001-2013 microchip technology inc. notes:
? 2001-2013 microchip technology inc. ds21669d-page 37 mcp6041/2/3/4 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device : mcp6041: single op amp mcp6041t single op amp (tape and reel for sot-23, soic, msop) mcp6042 dual op amp mcp6042t dual op amp (tape and reel for soic and msop) mcp6043 single op amp w/ chip select mcp6043t single op amp w/ chip select (tape and reel for sot-23, soic, msop) mcp6044 quad op amp mcp6044t quad op amp (tape and reel for soic and tssop) temperature range: i = -40c to +85c e = -40c to +125c package: ch = plastic small outline transistor (sot-23), 6-lead (tape and reel - mcp6043 only) ms = plastic micro small outline (msop), 8-lead ot = plastic small outline transistor (sot-23), 5-lead (tape and reel - mcp6041 only) p = plastic dip (300 mil body), 8-lead, 14-lead sl = plastic soic (150 mil body), 14-lead sn = plastic soic (150 mil body), 8-lead st = plastic tssop (4.4 mm body), 14-lead examples: a) mcp6041-i/p: industrial temperature, 8ld pdip package. b) mcp6041t-e/ot: tape and reel, extended temperature, 5ld sot-23 package. a) mcp6042-i/sn: industrial temperature, 8ld soic package. b) mcp6042t-e/ms: tape and reel, extended temperature, 8ld msop package. a) mcp6043-i/p: industrial temperature, 8ld pdip package. b) mcp6043t-e/ch: tape and reel, extended temperature, 6ld sot-23 package. a) mcp6044-i/sl: industrial temperature, 14ld soic package. b) mcp6044t-e/st: tape and reel, extended temperature, 14ld tssop package.
mcp6041/2/3/4 ds21669d-page 38 ? 2001-2013 microchip technology inc. notes:
? 2001-2013 microchip technology inc. ds21669d-page 39 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2001-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62077-042-9 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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